FPGA Design/Verification Engineer - Secret Clearance

Are you an FPGA Design/Verification Engineer who is looking to join one of the top companies within the Aerospace and Defense Industry?

Are you looking to further your career and grow?

Do you have experience with UVM verification methodology?

If you answered yes to those three questions, then apply today!

Acara Solutions is seeking highly qualified candidates to work Remotely with our client in Littleton, CO. Interested?

Here's what you'd do:

• Responsible for FPGA verification using the UVM methodology and following the client processes.
• Work with low SWaP, radiation-hardened, space-rated devices.
• Devise a unique verification plan for a given design.
• Use SystemVerilog and Universal Verification Methodology (UVM) to verify a design in a Linux-based high-performance computing environment.
• Develop requirements, test cases, build test benches, generate reports, and document verification results.
• Work with an independent design team to document and resolve bugs found in the design.
• Support all aspects of ASIC and FPGA development, to include architecture, design, and analysis.
• Support technical reviews, and be able to present to internal and external stakeholders.

Here's what you'll get:

• Pay rate: $89.13/hour
• Hours: 4/10-1st Shift
• Length: Temp (10 Months)

Sound like a good fit?

APPLY TODAY

About Acara Solutions

Acara is a premier provider of recruiting and workforce solutions we help companies compete for talent. With a legacy of needs in various industries worldwide, we partner with clients, listen to them, and customize visionary talent solutions that drive desired business outcomes. We leverage decades of experience to deliver contingent staffing, direct placement, executive search, and workforce services worldwide.

• Bachelor's Degree
• Minimum of 8 years experience with UVM verification methodology
• Minimum of 8 years experience with developing test cases based on given requirements.
• Minimum of 8 years experience with building test benches for FPGA / ASIC designs to provide randomized stimulus.
• Minimum of 8 years experience with identifying and implementing necessary test exclusions.
• Minimum of 8 years experience with generating coverage reports (code and functional)
• Minimum 8 years of Hands-on experience with UVM and closing functional and code coverage

Additional Information:

• Upon offer of employment, the individual will be subject to a background check and a drug screen.
• Active Secret DoD Clearance
• In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification form upon hire.
• Under the International Traffic in Arms Regulations (ITAR), all employees assigned to this client must provide documentation verifying their status as a 'U.S. Person', as defined in ITAR clause 120.15. A U.S. Person is a protected individual under the anti-discrimination provisions of U.S. immigration laws.