Principal Engineer

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Work with Business Units chip design team & Analog / Digital IP / Phy owners (e.g. 224G PAM4, 112G PAM4, HBM3/4) for new advanced node silicon (5nm, 3nm, 2nm..) chip floor plan & IP bump pattern design and optimization for package design requirements (e.g. layer-count, stack-up, escape architecture, BGA pattern development, s-parameter extraction/comprehension and optimization [RL, NEXT/FEXT, IL etc.], and power integrity [PI] requirements)

Work with business unit marketing and IC design teams to select the optimum package solution on cost, performance, manufacturability, and reliability for new advanced silicon node products monolithic, 2.5D & Co-Packaged Optics (5nm, 3nm, 2nm and beyond)

• Experienced w/ hands-on design & development of advanced large multi-reticle size 2.5D (Si Interposer, RDL interposer, & Bridge) packages (3D is a plus)
• Work with IC design, system design, package SI/PI & thermal engineering teams to design custom packages using Cadence APD
• Ensure designed packages meet CPI, SI/PI, and stringent thermal requirements (2000W ) of advanced node cutting edge silicon products
• Research, develop, and productize new materials such as TIM, build-up-film, underfill etc. in support advanced node silicon (7nm & 5nm) POR definition including bump cell definition (metal scheme, geometry, metallurgy etc.)
• Manage IC packaging activity from concept through development, qualification through high volume production
• Be a specialist and able to define assembly BOM, process, troubleshoot, support on packaging issues on new advanced technology
• Implement, fine-tune, and productize newly developed technologies into HVM
• Create package design documentation and assembly instructions
• Work close with QA and customers to resolve quality issues
• Interface with packaging assembly and substrate suppliers for new product bring-up, qualification and production ramp
• Interface with other operations functional groups such as product engineering, foundry, test, and QA
• Participate in package technology development and/or other business productivity projects which have broad team impact (e.g. assembly process enhancement, new interposer technology/structure development etc.)
• Interface with tier #1 external customers for custom ASIC programs or as needed for development support, quality and/or other issue resolution
• Support NPI bring-up, pkg qual, and sustain support in production multi-source activities for capacity, cost, & manufacturing flexibility needs

Job Requirements

• Experience: Bachelors and 12 years of related experience; at this level a post-graduate degree is typically expected or Masters degree and 10 years of related experience or PhD and 7 years of related experience
• Experienced managing layout engineers (internal & external) to drive very high-quality complex designs to completion on time consistently
• Deep understanding of signal integrity and power integrity concepts such as characteristic impedance, s-parameters (RL, IL, FEXT/NEXT etc.), power plane impedance profile requirements and optimization etc.
• Strong authority on Cadence APD for custom substrate design
• Hands-on expertise of advanced and new assembly processes for flipchip, MCM packages, and 2.5D for advanced node silicon products (7nm, 5nm and beyond)
• Good understanding of materials as related to Chip Packaging Interaction (CPI)
• Familiarity with wafer BEOL as related to CPI (top metal, AP, passivation, UBM, bumping etc.)
• Knowledge of advanced substrate manufacturing/process is a must (e.g. SAP/mSAP, PSPI w/ Cu RDL etc.)
• In depth knowledge of failure analysis techniques on advanced node silicon (7nm, 5nm etc.) products with ELK and MiM structures
• Conceptual knowledge of package cost structure
• Strong project management, communication, and leadership skills
• Must have knowledge of GD&T and be able to read/comprehend mechanical drawings
• Good understanding of manufacturing and quality engineering fundamentals (DOE, process capability indices, etc.)
• Job requirements are broad; the candidate must be able to expand and grow in multiple disciplines (manufacturing/quality, materials, electrical, thermal, and mechanical)
• Track record of innovation and subject matter expertise through journal publications and/or patent awards is desired

Familiarity with advanced technologies such as 3D patterned structures such as inductors in package substrate, embedding etc. are

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $111,000- $185,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

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