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ASIC design engineer

Central Business Solutions, Inc
Santa Clara, CA Full Time
POSTED ON 4/6/2024
Position Role/Tile: ASIC design engineer
Location: Santa Clara, CA .



What you'll be doing:
  • As part of the clock auditor team, you will be responsible for developing and running checks for a project. Understanding the goal of the clock checks will help you understand the impact of the check on clock structure.
  • The job requires understanding of perl/tcl/primetime to develop and work on clock checks.
  • We encourage our team members to determine factors that impact the quality of the clock design throughout the project. We expect you to identify issues. Collaborate with our multi-functional teams to resolve issues and deliver high quality clocks for GPU/SOC/CPU products from Nvidia. The checks include understanding of clock transitions, noise, duty cycle, clock uncertainty, and their interaction with NVIDIA clocking design. The successful resolution of these checks help us generate high performance products.
  • We are continuously looking for suggestions to improve the runtime of the checks for the sophisticated designs at NVIDIA.
What we need to see:
  • BS or MS(preferred) in EE. 2 to 5 years of relevant work experience or equivalent experience.
  • Familiar with tcl, primetime and Perl scripting is helpful.
  • Your ability to group errors together for quicker debug by the engineers will be beneficial.
  • Familiar with running scripts to perform synthesis and debugging timing sessions
  • Following up on issues with the team members and getting issues resolved is a benefit.
Ways to stand out from the crowd:
  • Previous experience working with multi-functional teams is desirable.
  • Summarizing issues in a concise way for engineers to review is beneficial.


Central Business Solutions, Inc,
37600 Central Ct.
Suite #214
Newark, CA 94560.

Salary.com Estimation for ASIC design engineer in Santa Clara, CA
$91,531 to $113,752
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