What are the responsibilities and job description for the RTL Designer (VHDL/Verilog) position at COMTEC INFORMATION SYSTEMS?
Job Title: Engineering - Engineer Digital 3
Work Location: Manhattan Beach - 1 Sp Park M5 (K468)
Duration: 12 Months
Job Description:
Experienced RTL designer (VHDL or Verilog) for FPGA and digital ASIC designs. Main responsibility include:
- Recent experience in implementing RTL designs when given requirements.
- Determines architecture design, logic design, and system simulation.
- Defines module interfaces/formats for simulation.
- Prepare detailed design documentation
- HDL coding, logical equivalency checking, static timing analysis, CDC, linting
- Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use.
- Integration of third-party IP
- Create self-checking and reusable test benches from scratch, utilizing Object Oriented Programming concepts: Inheritance, Polymorphism, etc.
- Develop Functional Coverage Models and closing Code Coverage
Desired Skills/Experience:
- Familiar with Xilinx Vivado or Microsemi Libero
- Experience in scripting languages: Make, Perl, Python, shell scripts, etc.
- Experience in Revision Control Systems: Subversion (SVN), CVS, Git.
- Work experience writing architectural design documents (micro-architecture documents with timing diagrams, detailed design blocks, etc.).
- Work experience performing RTL synthesis.
- Work experience performing Static Timing Analysis and correcting timing violations.
- Work experience creating a self-checking simulation test benches from scratch.
Job Types: Full-time, Contract
Pay: $90.00 - $115.00 per hour
Schedule:
- Monday to Friday
Experience:
- RTL Design: 1 year (Preferred)
- VHDL: 1 year (Preferred)
- Verilog: 1 year (Preferred)
- HDL Coding: 1 year (Preferred)
Work Location:
- One location
Work Remotely:
- No
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