Senior Design Verification Engineer
Job Posting for Senior Design Verification Engineer at Encore Semi, Inc.
Job Title: Senior Design Verification Engineer
Location: 100% remote / work from home
Full-time: Salary Benefits Bonuses or Contractor (Corp-to-Corp)
Work Status: US Citizen or US Permanent Resident
Summary:
We are currently looking for ASIC Design Verification Engineers who will be verifying PCI Express design using latest UVM standard and develop comprehensive testplan to ensure coverage closure. The position allows exposure to all aspect of ASIC design stages. A strong C /System Verilog language and problem-solving skill is required. Good understanding of PCI Express and Computer Architecture is preferred. Other technical knowledge such as Verilog, Perl, and OVL would be beneficial for testbench/simulation debug.
Responsibilities:
• Writing/Implementing/Reviewing Test Plans
• Triaging and Debugging Regressions
• Analyzing Functional, Code, and Test Plan Coverage
• Conducting and participating in Code Reviews
• Writing, Modifying, and Maintaining Random and Directed Test Cases and Libraries in SystemVerilog/UVM
• Implementing Assertions, Checkers, and Monitors
• Utilizing In-House and 3rd Party IP/SOC CAD and EDA Tools for Design Verification
Requirements:
• Digital Design in RTL, Verilog HDL
• Testbench Architecture, SystemVerilog, OVM/UVM/VMM
• C/C , Java or other object-oriented programming language
• Perl, Ruby, Shell-scripting, UNIX/LINUX Environment
• VCS, NCSIM, Questa, or other simulator and associated waveform viewers such as Verdi
• PC System Architecture: PCI Express, HyperTransport, x86, ARM
• On-Chip Bus Interfaces and Architectures: AMBA AXI, OCP, PIPE
Education:
• BSEE or equivalent with 8 years of experience required
• MSEE or equivalent with 5 years of experience preferred
Location: 100% remote / work from home
Full-time: Salary Benefits Bonuses or Contractor (Corp-to-Corp)
Work Status: US Citizen or US Permanent Resident
Summary:
We are currently looking for ASIC Design Verification Engineers who will be verifying PCI Express design using latest UVM standard and develop comprehensive testplan to ensure coverage closure. The position allows exposure to all aspect of ASIC design stages. A strong C /System Verilog language and problem-solving skill is required. Good understanding of PCI Express and Computer Architecture is preferred. Other technical knowledge such as Verilog, Perl, and OVL would be beneficial for testbench/simulation debug.
Responsibilities:
• Writing/Implementing/Reviewing Test Plans
• Triaging and Debugging Regressions
• Analyzing Functional, Code, and Test Plan Coverage
• Conducting and participating in Code Reviews
• Writing, Modifying, and Maintaining Random and Directed Test Cases and Libraries in SystemVerilog/UVM
• Implementing Assertions, Checkers, and Monitors
• Utilizing In-House and 3rd Party IP/SOC CAD and EDA Tools for Design Verification
Requirements:
• Digital Design in RTL, Verilog HDL
• Testbench Architecture, SystemVerilog, OVM/UVM/VMM
• C/C , Java or other object-oriented programming language
• Perl, Ruby, Shell-scripting, UNIX/LINUX Environment
• VCS, NCSIM, Questa, or other simulator and associated waveform viewers such as Verdi
• PC System Architecture: PCI Express, HyperTransport, x86, ARM
• On-Chip Bus Interfaces and Architectures: AMBA AXI, OCP, PIPE
Education:
• BSEE or equivalent with 8 years of experience required
• MSEE or equivalent with 5 years of experience preferred
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Salary.com Estimation for Senior Design Verification Engineer in Los Angeles, CA
$128,101 to $156,941
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