Senior Design Verification Engineer
Job Posting for Senior Design Verification Engineer at Encore Semi, Inc.
Job Title: Senior Design Verification Engineer
Location: San Jose, CA
Status: US Citizen or US Permanent Resident only
Responsibilities:
• Advanced UVM based test bench development and debugging
• Defining, documenting, developing and executing RTL verification test/coverage at system level
• Performance verification and power-aware verification
• Triaging Regressions, Debugging RTL designs in Verilog and SystemVerilog
• Help improve and refine verification process, methodology, and metrics
• UVM expertise on complex SoC projects from test bench development to verification closure
Requirements:
• 10 years of design and verification experience and a plus in interconnect verification experience
• Verification flow enhancements using a scripting language such as Shell scripts, Python & JavaScript
• Strong RTL (Verilog) and UVM/C test bench debugging skills
• Experience integrating vendor provided VIPs for unit and system level verification
• Experience with Arm AMBA protocols
• Experience with Cadence, Synopsys, Mentor logic simulators
• Verification flow enhancements using a scripting language such as Shell scripts, Python & JavaScript
• This opportunity involves high performance, low power designs on a highly visible project
• BS/MS degree in EE, CS, or equivalent
---
The anticipated annual base salary for this position is between $140,000 - $180,000 which also includes a comprehensive benefits package.
Location: San Jose, CA
Status: US Citizen or US Permanent Resident only
Responsibilities:
• Advanced UVM based test bench development and debugging
• Defining, documenting, developing and executing RTL verification test/coverage at system level
• Performance verification and power-aware verification
• Triaging Regressions, Debugging RTL designs in Verilog and SystemVerilog
• Help improve and refine verification process, methodology, and metrics
• UVM expertise on complex SoC projects from test bench development to verification closure
Requirements:
• 10 years of design and verification experience and a plus in interconnect verification experience
• Verification flow enhancements using a scripting language such as Shell scripts, Python & JavaScript
• Strong RTL (Verilog) and UVM/C test bench debugging skills
• Experience integrating vendor provided VIPs for unit and system level verification
• Experience with Arm AMBA protocols
• Experience with Cadence, Synopsys, Mentor logic simulators
• Verification flow enhancements using a scripting language such as Shell scripts, Python & JavaScript
• This opportunity involves high performance, low power designs on a highly visible project
• BS/MS degree in EE, CS, or equivalent
---
The anticipated annual base salary for this position is between $140,000 - $180,000 which also includes a comprehensive benefits package.
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Salary.com Estimation for Senior Design Verification Engineer in San Jose, CA
$144,315 to $176,806
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