What are the responsibilities and job description for the SoC Design Engineer position at Intel?
Job Description
Intel is a global leader, creating world-changing technology that enables progress and enriches lives. We are at the intersection of several technology inflections - artificial intelligence, 5G network transformation and the rise of the intelligent edge- together will shape the future of technology.
Intel's Programmable Solutions Group (PSG) has been delivering industry leading custom logic solutions to customers since inventing the world's first programmable logic device in 1984. The mission of PSG is to drive the future for Field Programmable Gate Array (FPGA) and Intel® eASIC™ technology around the globe. Within PSG, you'll be surrounded by some of the brightest minds and engineers in the world.
This is to fill a position in PSG Programmable Technology Engineering (PTE) group. He/she will be leading cross-org effort in modeling and improving PSG product SEL/SEU/other reliability performance through design-technology co-optimization (DTCO).
As a SOC Design Engineer your responsibilities will include:
- Work as a highly proficient technical individual contributor.
- Lead design-technology and system-technology co-optimizations to ensure products are meeting quality targets in the areas of SEL/SEU/other reliability measures.
- Develop and validate methodology to model SEU/SEL performance for next generation FPGA through leading cross-org and cross-business unit collaborations.
- Drive process technology pathfinding on reliability requirements for next generation products to meet quality requirements.
Qualifications
This position is not eligible for Intel sponsorship.
Minimum Education Requirement
Masters' degree in Electrical Engineering
Minimum Requirements
5 years of experience in the semiconductor industry in the following areas :
- Deep understanding of semiconductor/CMOS integrated circuit SEL/SEU/reliability issues and impact on products in certain use conditions.
- 5 years of experience on product SEL/SEU/reliability characterization and design technology co-optimization to meet product quality target.
- Experience incomplementary metal-oxide-semiconductor (CMOS) device physics and transistor and BEOL spice models, DRC and DFM rules for advanced processes (10nm, 7nm, 5nm, and beyond).
- Experience on circuit design/verification and memory.
- Experience with industry EDA tools such as Hspcie, Spectre, Finesim StarRC, and layout tools including Cadence Virtuoso.
Preferred Qualifications
- Custom digital design/optimization, memory design, product reliability experience and knowledge on SEL/SEU/SDE.
- Experience with script such as Perl, Python, etc.
Inside this Business Group
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.
Other Locations
US,OR,Hillsboro;US,CA,Santa Clara
Covid Statement
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in US, California: $156,410.00-$250,410.00
*Salary range dependent on a number of factors including location and experience
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Intel is a global leader, creating world-changing technology that enables progress and enriches lives. We are at the intersection of several technology inflections - artificial intelligence, 5G network transformation and the rise of the intelligent edge- together will shape the future of technology.
Intel's Programmable Solutions Group (PSG) has been delivering industry leading custom logic solutions to customers since inventing the world's first programmable logic device in 1984. The mission of PSG is to drive the future for Field Programmable Gate Array (FPGA) and Intel® eASIC™ technology around the globe. Within PSG, you'll be surrounded by some of the brightest minds and engineers in the world.
This is to fill a position in PSG Programmable Technology Engineering (PTE) group. He/she will be leading cross-org effort in modeling and improving PSG product SEL/SEU/other reliability performance through design-technology co-optimization (DTCO).
As a SOC Design Engineer your responsibilities will include:
- Work as a highly proficient technical individual contributor.
- Lead design-technology and system-technology co-optimizations to ensure products are meeting quality targets in the areas of SEL/SEU/other reliability measures.
- Develop and validate methodology to model SEU/SEL performance for next generation FPGA through leading cross-org and cross-business unit collaborations.
- Drive process technology pathfinding on reliability requirements for next generation products to meet quality requirements.
Qualifications
This position is not eligible for Intel sponsorship.
Minimum Education Requirement
Masters' degree in Electrical Engineering
Minimum Requirements
5 years of experience in the semiconductor industry in the following areas :
- Deep understanding of semiconductor/CMOS integrated circuit SEL/SEU/reliability issues and impact on products in certain use conditions.
- 5 years of experience on product SEL/SEU/reliability characterization and design technology co-optimization to meet product quality target.
- Experience incomplementary metal-oxide-semiconductor (CMOS) device physics and transistor and BEOL spice models, DRC and DFM rules for advanced processes (10nm, 7nm, 5nm, and beyond).
- Experience on circuit design/verification and memory.
- Experience with industry EDA tools such as Hspcie, Spectre, Finesim StarRC, and layout tools including Cadence Virtuoso.
Preferred Qualifications
- Custom digital design/optimization, memory design, product reliability experience and knowledge on SEL/SEU/SDE.
- Experience with script such as Perl, Python, etc.
Inside this Business Group
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.
Other Locations
US,OR,Hillsboro;US,CA,Santa Clara
Covid Statement
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in US, California: $156,410.00-$250,410.00
*Salary range dependent on a number of factors including location and experience
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
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