Design Verification Engineer

Intuitive
Sunnyvale, CA Full Time
POSTED ON 4/12/2022 CLOSED ON 10/1/2022

Job Posting for Design Verification Engineer at Intuitive

Company Description

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Job Description

Primary Function of Position:

·         Verification of FPGA’s on daVinci systems for RTL functional correctness.

 Roles & Responsibilities:

  • Responsibilities includes starting from testplanning to closing verification using coverage metrics.
  • Involves testbench development from scratch or modification to existing testbench infrastructure for verifying new features.
  • Work closely with the design team to review specifications and architecture, extract features, define verification plan & coverage model.
  • Directed/constrained random test generation, failure analysis and resolution, coverage analysis.
  • Debugging failures, bug tracking, and analyze and close coverage.

Qualifications

Skills, Experience, Education, & Training:

  • Advanced knowledge of HVL methodology (UVM).
  • Expertise in HVL and HDL (SystemVerilog, Verilog).
  • Experience defining coverage space and writing coverage model.
  • Experience with SystemVerilog Assertion (SVA) is a plus.
  • Team player with excellent communication skills and the desire to take on diverse challenges.
  • Experience writing scripts in languages such as Perl/Python.
  • Solid verification skills in problem solving, constrained random testing, and debugging.
  • Experience with Veloce or other HW acclerators and Formal is a plus.

Preferred Job Experience:

·         0-5 years of experience

Additional Information

All your information will be kept confidential according to EEO guidelines.

Due to the nature of our business and the role, please note that Intuitive and/or your customer(s) may require that you show current proof of vaccination against certain diseases including COVID-19.  Details can vary by role.

Intuitive is an Equal Employment Opportunity Employer. We provide equal employment opportunities to all qualified applicants and employees, and prohibit discrimination and harassment of any type, without regard to race, sex, pregnancy, sexual orientation, gender identity, national origin, color, age, religion, protected veteran or disability status, genetic information or any other status protected under federal, state, or local applicable laws.

We will consider for employment qualified applicants with arrest and conviction records in accordance with fair chance laws.

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Salary.com Estimation for Design Verification Engineer in Sunnyvale, CA
$149,326 to $190,642
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