ASIC Design Engineer Intern

Marvell
Santa Clara, CA Intern
POSTED ON 11/25/2022 CLOSED ON 12/1/2022

Job Posting for ASIC Design Engineer Intern at Marvell

About Marvell

At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world's leading technology companies for 25 years, we move, store, process and secure the world's data with semiconductor solutions designed for our customers' current needs and future ambitions. Through a process of deep collaboration and transparency, we're ultimately changing the way tomorrow's enterprise, cloud, automotive, and carrier architectures transform-for the better.

The data infrastructure that our customers build has never been more critical to our global economy. It's what's keeping the world connected, businesses running, and information flowing. If you're ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.

The Opportunity

Datacom PHY DSP

Job Responsibilities:

* ASIC design engineer responsible for the design, verification and evaluation of digital circuits in high-speed data communication ICs
* The candidate will be involved in engineering implementation spec writing from system requirements, RTL design, verification, synthesis, static timing analysis
* Improve the design methodology and flow
* RTL designs for PCIe Retimer.
* Collaborate with Architect/DV/FW/AE teams
* Provide the support to the product teams, for both pre and post-silicon

Requirements:

Selected student should be working towards a Bachelor/Master/PhD in Computer Science, Electrical Engineering or related fields

Good personal communication skills and team working spirit

Hardworking and motivated to be part of a highly competent design team

Must be proficient in the following skills:

* Fundamental concepts in digital logic design
* Concepts of digital logic timing analysis
* Verilog/VHDL coding and Lint tools
* Strong Perl and Tcl scripting skills
* PCIe experience
* Micro-controller 8051 or ARM Cortex experience
* Synthesis using Synopsys or Cadence tools
* Timing analysis using Primetime

The Perks

With competitive compensation and great benefits, you will enjoy our workstyle within an incredible culture. We'll give you all the tools you need to succeed so you can grow and develop with us. For additional information on what it's like to work at Marvell, visit our Careers page.

Your Future

Marvell provides a work environment that promotes employee growth and development. We are searching for an individual who wants to grow with the company and will strive to improve performance. If you are driven, personable, and energetic, there will be additional opportunities for you here at Marvell.

At Marvell, we are doing our part to help keep our communities and our teams safe. As part of our efforts to address the Covid pandemic and future epidemics, you may be required at any time by our policies or applicable laws to provide proof of applicable vaccination or to present negative test results.

This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [ Email address blocked ] - Click here to apply to ASIC Design Engineer Intern or
408-222-3604
.

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Hourly Wage Estimation for ASIC Design Engineer Intern in Santa Clara, CA
$61.74 to $73.48
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