Package Design Engineer

Micross Components
Melville, NY Full Time
POSTED ON 8/27/2023 CLOSED ON 9/22/2023

What are the responsibilities and job description for the Package Design Engineer position at Micross Components?



Essential Duties and Responsibilities:

The primary responsibilities will include the entire IC package design flow, including layout, parasitic extraction, optimization, tape-out, and bench validation

Work with IC design, system design, package SI/PI & thermal engineering teams to design custom interposer and substrates

Work with SoC design teams to optimize die floorplan, bump patterns and interposer / substrate stack up

Work with IC design team to define IC package requirements

Design package layout using standard CAD tools

Extract package parasitics and conduct PI/SI analysis

Work with IC designers on power and signal integrity analyses of new power converter designs

Documentation and release in appropriate archival system

Preferred Knowledge, Skills, And Abilities

Layout:

Allegro Package Designer Plus- Package layout tools for designing the package and generating artwork for fabrication.

Analysis:

Sigrity Advanced SI II: Analysis tools for Signal integrity of parallel busses ( DDRx) and serial links (PCIe Gen x), including Package and PCB effects

Sigrity Advanced PI II: Power Integrity tools ( IR drop, Impedance Profile, capacitor optimization) including Package and PCB effects

Clarity Advanced IC Package Extraction Suite: 3D FEM solver and S-Parmenter extraction, Package optimization for Resistive and Inductive paths, Extraction of Inductance and Capacitance matrices for IBIS Models, 2.5D parameter extraction, and Package Spice model extraction.

Celsius Thermal Solver v8. This provides access to Celsius 2.5D FEA and 3D FEA solvers

RF / Microwave Design

AWR, Momentum and HFSS Software Circuit, system, and EM simulation for RF/microwave product development

Requirements

Qualifications

Bachelors degree in Electrical Engineering, or other semiconductor packaging related discipline.

8 to 10 years of experience in semiconductor packaging design, modeling, and simulations

Experience on interposer and substrate layouts and design in advanced package technologies

Experience with 2.5D, 3D package design

Experience with design teams on floor plan, bump and layout optimization

Strong authority on Cadence Allegro Package Designer (APD)Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated

Record of success in cross-functional team environment

Good experience with SI/PI tools for package level extraction/simulation

Benefits

Medical, Dental, and Vision

401k

Company Paid Basic Life Insurance, STD, and LTD

Vacation Time

Sick Time

Holidays

Tuition Reimbursement

Pet Insurance

Legal Insurance offered through Allstate

Critical Illness, Hospitalization and Accident Insurance offered through Allstate

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