Pad/IO Circuit Design Engineer

Pad/IO Circuit Designer This vacancy is within the IO design team of the MMEDE Mixed-Signal IP organization, a team responsible for designing, integrating, and supporting the IO libraries necessary for NXP Microcontrollers. Job Summary: IO library design and support from definition, through design, simulation, documentation, layout, verification, integration at SoC (including view support), silicon validation, and customer support Key Challenges: Balancing tradeoffs between high performance, low power, area, reliability, test access/testability and delivering a first time right, robust design. Working across cross functional teams to understand and address multiple sign-off criteria with IBIS, PISI, package co-simulation. Cross functional aspects: Work with Systems Engineering to establish specifications and design requirements. Collaborate closely with packaging, SoC Front/Back End, Test and Validation Teams, and Design Enablement to facilitated co-operability between these disciplines. Work closely with SoC team and key IP’s to handle integration of full chip Work closely with Test and Validation teams for silicon bring-up and validation of IP Work closely with Reliability Team, Modeling Teams, Design Process Teams when developing in new technologies or when developing new architectures Job Qualifications: BS in Electrical Engineering or other similar discipline with at least 10 years of relevant experience. MS in Electrical Engineering preferred (higher level education may substitute for some experience). Proven understanding of high speed and GPIO circuit design circuit fundamentals, design tools and methodologies. Understanding of compromises needed with on-board components such as regulators, passives and an understanding of multiple sign off criteria with IBIS, PISI, package co-simulations. Deep understanding of power, area and frequency tradeoffs. Understanding of FinFet technologies is a must with design experience preferred. Knowledge and experience in working on various IC process technologies, design flows, reliability design methodology such as aging EM/IR, and familiarity with ESD co-design Experience with Cadence OA tool set for schematic entry and layout creation Job location: Austin, TX NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.