Top Division Engineering Executive jobs in Phoenix, AZ

We Are:

The Silicon Design group is a diverse team of world class silicon engineers. We have 100 years of cumulative hands-on experience in architecture, logic design, verification, physical design, emulation and firmware. We use the latest silicon technologies and processes to help our clients create well-designed solutions to highly complex challenges. We are designing and developing next-generation, high performance SoCs, supporting our clients in their drive to deliver their product vision to their users. We are involved in all aspects of chip design from definition and architecture through to verification and signoff. Accenture engineers are true Silicon to SW Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market.

You Are:

An experienced Emulation and Prototyping Engineer

The Work:

• Port ASIC and IP RTL code to prototyping and emulation platforms (Zebu/HAPSs, Palladium/Protium)
• Build model from released RTL
• Generate loadable image(s) for target prototyping and emulation platform
• Run sanity tests to qualify release of the image(s)
• Release the emulation/prototyping images to various teams doing functional validation, firmware development and design verification
• Assist debug of failures with stakeholder by providing instrumented models and captured waveforms extracted from in-circuit debug logic
• Coordinate with EDA and prototyping tools team to validate implementation flows

• A minimum 5 years of experience in Emulation, Prototyping or FPGA design and verification using System Verilog/Verilog/VHDL
• A minimum of 5 years of experience with porting ASIC/IP RTL to Emulation platforms: Zebu/HAPSs, Palladium/Protium
• Bachelors Degree or equivalent (12 years) work experience (If an, Associates Degree with 6 years of work experience)

Bonus points if:

• Unix/Linux development environments and scripting languages like Tcl, Python, C-shell
• Logic simulation: VCS/Xcelium
• Strong knowledge of Complete Design Cycle to understand the Different IP designs to integrate In the build
• Good knowledge of SoC design methodologies and technologies, with experience in the complete design validation cycle
• Knowledge of key protocols like PCIe, USB, Ethernet, AMBA, UART, DDR, flash memories and their usage in SoC environments
• Experience with CPU integration is a big plus, especially ARM/RISC-V CPU
• Knowledge of CoreSight/UltraSoC debug infrastructure integration
• Familiarity with IO's such as MIPI CSI & DSI, USB, PCIE, LPDDR
• Experience with lab system debug with logic analyzers, scopes, meters etc
• SoC experience with bare-metal code
• Post silicon bringup

Compensation at Accenture varies depending on a wide array of factors, which may include but are not limited to the specific office location, role, skill set, and level of experience. As required by local law, Accenture provides a reasonable range of compensation for roles that may be hired in California, Colorado, New York or Washington as set forth below.
We accept applications on an on-going basis and there is no fixed deadline to apply.

Role Location Annual Salary Range

California $93,400 to $258,500

Colorado $93,400 to $223,300

New York $86,500 to $258,500

Washington $99,500 to $237,800

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