Actively contribute to the architectural definition of the design and chip integration and work with business and application team to define specifications for upcoming IC's.
January 02, 2020
Understand the requirements and architect a digital CCA solution against those requirements including the use of DSP, Microcontroller, FPGA, ASIC, CPLD, ADC, DAC, Point of Load (POL), SERDES, Serial (I2C, SPI, etc), and volatile/non-volatile memory (DDRx, SRAM, ROM, Flash, etc) components.
March 06, 2020
Design and develop user interfaces and applications by setting expectations and feature priorities throughout development life cycle, determining design methodologies and tool sets, completing programming using languages and software products, and designing and conducting tests.
April 18, 2020
Provide Architecture reviews to evaluate how to reroute a connection or find an alternative solution if bandwidth is not available in a location, coordinating with the Defense Information Systems Agency (DISA), local site representatives, Regional Information Technology (IT) staff and the Defense Health Agency (DHA) Medical Circuit Management Office (MCMO).
April 25, 2020
Demonstrated knowledge of and experience with implementing Sandia policies affecting research, design, and development activities, projects, or initiatives.
May 05, 2020
Test and validate designed layouts to ensure compatibility with Laser Diode system, customer specifications and environmental requirements before implementation to production.
May 19, 2020
Developing ESD libraries and publishing ESD guidelines for circuit, layout and package designers based on test chips and foundry data - TLP/VFTLP testing for design and debug - Silicon validation and debugging ESD failures along with RMA analysis - ESD co-design by working closely with IO, Analog, RF design/layout engineers & Packaging team - Working with Product testing and Reliability teams for qualification and meeting JEDEC specifications for ESD and Latch-up.
May 30, 2020