Developing ESD libraries and publishing ESD guidelines for circuit, layout and package designers based on test chips and foundry data - TLP/VFTLP testing for design and debug - Silicon validation and debugging ESD failures along with RMA analysis - ESD co-design by working closely with IO, Analog, RF design/layout engineers & Packaging team - Working with Product testing and Reliability teams for qualification and meeting JEDEC specifications for ESD and Latch-up.
September 08, 2021
Generate innovative solutions that can be brought to market and protected by patents.
September 24, 2021
Support technical audits and reviews as a technical authority, consultant, or customer representative, to perform independent verification and validation in areas such as hardware design, electronic PM&P pedigree, producibility, technology, and manufacturing readiness.
October 28, 2021
Demonstrated knowledge of and experience with implementing Sandia policies affecting research, design, and development activities, projects, or initiatives.
November 12, 2021
Test and validate designed layouts to ensure compatibility with Laser Diode system, customer specifications and environmental requirements before implementation to production.
November 18, 2021
Actively contribute to the architectural definition of the design and chip integration and work with business and application team to define specifications for upcoming IC's.
December 17, 2021
Provide Architecture reviews to evaluate how to reroute a connection or find an alternative solution if bandwidth is not available in a location, coordinating with the Defense Information Systems Agency (DISA), local site representatives, Regional Information Technology (IT) staff and the Defense Health Agency (DHA) Medical Circuit Management Office (MCMO).
January 06, 2022