Develop Unit level and Subsystem level test plans and verification environment components for functional verification and performance verification by writing randomized and directed test cases and coverage using SystemVerilog and UVM.
June 03, 2020
Create coverage driven verification plans from specifications, review and refine to achieve coverage targets.
June 19, 2020
Design verification experience (developing test plan, test bench, tests, assertions, functional and code coverage, and debugging tests and designs).
June 23, 2020
Generate random/directed test cases, debug failures, run regressions, evaluate and achieve coverage targets for the design.
August 04, 2020
Collaborate with SW, FW, emulation and product testing teams to aid in the verification and debug of boot code, drivers, and test vector generation.
September 03, 2020
Functional Safety experience (ISO26262, FMEDA and feature tracking, secure connectivity, sensor for safety, safety verification automation, commercial functional safety tools, fault campaign, safety analysis, etc.
September 05, 2020
Require additional responsibilities such as running and triaging regressions, tracking bugs.
September 14, 2020
Hands on experience with CAD tool management to support small team with design and verification needs.
September 19, 2020
Understand details of High Throughput SoC Architecture, standard SoC peripherals such as SPI, I2C, UART, Timers, DMA, memory management schemes, low power spec and power aware testing, multi-processor systems, DDR, PCIe, PLL, debug infrastructure, on-chip security verification, power up schemes.
September 24, 2020
Build chip level verification infrastructure with advanced verification methodology and develop test-plans to achieve coverage goals.
October 09, 2020