Senior Verification Engineer

3K Technologies
Austin, TX Other
POSTED ON 6/6/2023 CLOSED ON 6/23/2023

What are the responsibilities and job description for the Senior Verification Engineer position at 3K Technologies?

Job Description

Job Title: Senior Verification Engineer

Location: Austin, TX (onsite)

Type: C2C

 

Job Description:

The candidate would participate on a team of design verification, architects, and design engineers, working closely with other team members to understand and verify the functionality of the design within the context of the unit, block, and overall system. The candidate would be responsible for carefully documenting and executing test plans consisting of directed and random tests to be run under simulation and hardware acceleration and to add and collect functional coverage. Experience with hardware modelling, assertions, coverage and formal verification methods are required. The candidate would be encouraged to adopt evolving verification methodologies used in the industry as well as develop custom techniques to functionally verify increasingly complex IP designs within ambitious schedules.

 

Key Responsibilities:

  • Use advanced verification methodologies for the verification of complex designs.
  • Work with existing tools/flows or develop new tools/flows to complete the assigned verification task.
  • Compose test and coverage plan, and validation vectors to ensure functional completeness.
  • Build System Verilog and/or C/C models and test sequence libraries for simulation.
  • Build test bench, agents, monitors, and scoreboard for DUT.
  • Debug function/performance bugs of Display IP

 

Preferred Experience:

  • 5 years of experience in ASIC verification
  • Solid understanding of ASIC IP verification methodologies and processes
  • Must be proficient in Verilog and System Verilog language.
  • Must have working experience with UVM, OVM or equivalent.
  • Must be good at C/C programming and working in Linux and Windows environments.
  • Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation/emulation tools.
  • Must have ASIC design verification experience in test plans, test creation, and triage, coverage, and assertion, etc.
  • Must be proficient of script language like Perl, Python
  • Must have excellent writing and communication skills.
  • Must demonstrate strong analytical thinking and problem-solving skills with excellent attention to detail.
  • Must have good teamwork and interpersonal skills.
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Salary : $50 - $0

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