What are the responsibilities and job description for the ASIC Engineer III position at Actalent?
Silicon Digital Design/ASIC Engineer III (Fully Remote)
Job Description
Seeking a skilled Silicon DD Engineer III to join our client's team. This fully remote role involves collaborating on uarchitecture development and performing RTL coding for the next version of our graphics IP, which will be used in future AR products. The successful candidate will own ASIC IP RTL implementation for IP blocks, ensure RTL quality, collaborate with various teams for design and testing, and support integration into larger SOC environments.
Position: Silicon Digital Design Engineer
Location: Remote
Pay rate: $70-90/hour
Duration: 12 month contract (W2)
What are the top non-negotiable skill sets required for this role?
- Experience in RTL coding, synthesis and/or SoC Integration
- Experience in digital design Architecture
- Familiarity with Verilog, systemVerilog coding
Duties:
- Contribute to the development of efficient µArchitectures and contribute to ASIC digital µArchitecture, design and verification
- IPs integration
- Understand Design for Verification concepts
- Drive the top-level µArchitecture definition and develop the necessary RTL
- Drive the chip-level integration, verification plan development and verification
- Supervise the RTL-to-GDS flow and assist with synthesis and timing closure
- Support the test program development, chip validation and chip life until production maturity
- Work with FPGA engineers to perform early prototyping
- Support hand-off and integration of blocks into larger SOC environments
- Assist with Algorithm analysis, verification and improvement
- Contribute to ASIC digital architecture, design and verification
SKILLS
Must Have:
- 4 years of experience as a Digital Design Engineer and/or a Chip Lead
- Experience in RTL coding, synthesis and/or SoC Integration
- Experience in digital design Architecture
- BS Electrical Engineering/Computer Science or equivalent experience
- Experience with UPF based simulation flow
- System Verilog OVM/UVM experience
- Tcl and Python (or similar) scripting experience
- Experience in SoC integration and ASIC architecture
Nice to Have:
- Experience in DFT/Testability requirement and test program definition
- Experience using High Speed interfaces like PCIe, USB, MIPI
- FPGA design
- Tensilica DSP, TIE, CNN, fixed point, floating point, python.
- Experience with Power Aware GLS flow
- MSEE/CS or equivalent experience
Education
Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science
About Actalent
Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 30,000 consultants and more than 4,500 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500.
Diversity, Equity & Inclusion
At Actalent, diversity and inclusion are a bridge towards the equity and success of our people. DE&I are embedded into our culture through:
- Hiring diverse talent
- Maintaining an inclusive environment through persistent self-reflection
- Building a culture of care, engagement, and recognition with clear outcomes
- Ensuring growth opportunities for our people
The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.
If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing process due to a disability, please email actalentaccommodation@actalentservices.com for other accommodation options.
Salary : $70 - $80
