Physical Design (STA) Engineer
Job Posting for Physical Design (STA) Engineer at Ampcus, Inc
Role: Physical Design (STA) Engineer
Work Location: AUSTIN, TX Hybrid
Duration: 6 Months Assignment'
Job Description:
Full chip timing constraints development, full chip Static Timing Analysis and Signoff for a complex, multi-clock, multi-voltage SoC
Working with Systems and Application team to drive timing closure friendly SoC architecture and IO interfaces/IO pin.
Streamlining the timing signoff criterions, timing analysis methodologies and flows (critical path spice simulation etc.) and develop/enhance auto ECO generation scripts for timing closure.
Analyze and incorporate advance timing signoff flows (SSTA, LOCV Based STA, IR Drop aware STA) into SoC timing signoff flow.
Enhance existing entire timing flow from frontend (pre-layout) to backend (post-layout) at both chip level and block level.
Develop or enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from chip level to block level)
Ensure quality adherence during all stages of the project life cycle. Drive thorough analysis of existing processes and recommend and implement the process improvements to ensure 'Zero Defect' chips.
Active participation in post silicon validation, correlation and test activities using in-house test and validation lab.
Encouraging and influencing technological innovations in the team
Actively work as part of team both locally & also with remote and multi-site teams
Effectively lead highly energetic and intellectual team members through coaching and mentoring, provide technical direction for career planning, engage them on project issues, and manage change.
Key Skills
Self starter with 2-10 years of experience on SOC/Chip level/IP Timing closure and Signoff of high-speed complex design with multiple clocks and power domains with minimal supervision.
Expertise in developing and owning full chip Timing Constraints for a complex, multi-clock, multi-voltage SoCs. Exposure to Primetime (Synopsys is a must)
Expertise in protocol of Industry standard IO interfaces (e.g., DDR2, SDR, LPDDR, Flash, SPIs, USBHS, USBFS, JTAG, Display etc...)
Experience in analyzing failure in Functional and Test Gate-level simulations with back annotated data and interacting with Verification and DFT team in this respect.
Expertise in running STA analysis and achieving timing closure on multiple high performance and low power designs.
Experience in developing and supporting a fully automated STA scripts/flows.
Good understanding of deep submicron parasitic effects, crosstalk effects, newer statistical timing approaches
System Verilog, Python/TCL, Synopsys/Cadence tools
Thank you
Ampcus is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identify, national origin, age, protected veterans or individuals with disabilities.
Work Location: AUSTIN, TX Hybrid
Duration: 6 Months Assignment'
Job Description:
Full chip timing constraints development, full chip Static Timing Analysis and Signoff for a complex, multi-clock, multi-voltage SoC
Working with Systems and Application team to drive timing closure friendly SoC architecture and IO interfaces/IO pin.
Streamlining the timing signoff criterions, timing analysis methodologies and flows (critical path spice simulation etc.) and develop/enhance auto ECO generation scripts for timing closure.
Analyze and incorporate advance timing signoff flows (SSTA, LOCV Based STA, IR Drop aware STA) into SoC timing signoff flow.
Enhance existing entire timing flow from frontend (pre-layout) to backend (post-layout) at both chip level and block level.
Develop or enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from chip level to block level)
Ensure quality adherence during all stages of the project life cycle. Drive thorough analysis of existing processes and recommend and implement the process improvements to ensure 'Zero Defect' chips.
Active participation in post silicon validation, correlation and test activities using in-house test and validation lab.
Encouraging and influencing technological innovations in the team
Actively work as part of team both locally & also with remote and multi-site teams
Effectively lead highly energetic and intellectual team members through coaching and mentoring, provide technical direction for career planning, engage them on project issues, and manage change.
Key Skills
Self starter with 2-10 years of experience on SOC/Chip level/IP Timing closure and Signoff of high-speed complex design with multiple clocks and power domains with minimal supervision.
Expertise in developing and owning full chip Timing Constraints for a complex, multi-clock, multi-voltage SoCs. Exposure to Primetime (Synopsys is a must)
Expertise in protocol of Industry standard IO interfaces (e.g., DDR2, SDR, LPDDR, Flash, SPIs, USBHS, USBFS, JTAG, Display etc...)
Experience in analyzing failure in Functional and Test Gate-level simulations with back annotated data and interacting with Verification and DFT team in this respect.
Expertise in running STA analysis and achieving timing closure on multiple high performance and low power designs.
Experience in developing and supporting a fully automated STA scripts/flows.
Good understanding of deep submicron parasitic effects, crosstalk effects, newer statistical timing approaches
System Verilog, Python/TCL, Synopsys/Cadence tools
Thank you
Ampcus is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identify, national origin, age, protected veterans or individuals with disabilities.
Salary.com Estimation for Physical Design (STA) Engineer in Austin, TX
$102,974 to $127,465
If your compensation planning software is too rigid to deploy winning incentive strategies, it’s time to find an adaptable solution.
Compensation Planning
Enhance your organization's compensation strategy with salary data sets that HR and team managers can use to pay your staff right.
Surveys & Data Sets
Sign up to receive alerts about other jobs that are on the Physical Design (STA) Engineer career path.
Click the checkbox next to the jobs that you are interested in.
Sign up to receive alerts about other jobs with skills like those required for the Physical Design (STA) Engineer.
Click the checkbox next to the jobs that you are interested in.
-
Architecture Skill
-
Income Estimation: $90,485 - $115,217
-
Income Estimation: $100,485 - $142,568
-
-
Brand Management Skill
-
Income Estimation: $124,101 - $164,125
-
Income Estimation: $124,026 - $178,392
-
View Core, Job Family, and Industry Job Skills and Competency Data for more than 15,000 Job Titles
Skills Library
Job openings at Ampcus, Inc
Ampcus, Inc
Washington, DC
Full Time
Ampcus, Inc
Chantilly, VA
Full Time
Ampcus, Inc
Chantilly, VA
Full Time
Ampcus, Inc
Chantilly, VA
Full Time
Not the job you're looking for? Here are some other Physical Design (STA) Engineer jobs in the Austin, TX area that may be a better fit.
We don't have any other Physical Design (STA) Engineer jobs in the Austin, TX area right now.
Senior Physical Design Engineer
Chelsea Search Group, Austin, TX
Physical Design Engineer - DSP
Qualcomm Technologies, Austin, TX