What are the responsibilities and job description for the Static Timing Analysis Engineer position at Apple?
Summary
Posted:
Role Number:200441505
Do you love crafting elegant solutions to highly sophisticated challenges? Do you intrinsically see the importance in every detail? As a member of our dynamic Cellular group, you'll be at the heart of chip design! You'll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. As an ASIC STA engineer, you will be responsible for all aspects of timing including, working with designers for timing constraints generation, helping construct/modify flows, timing analysis and timing closure.
Key Qualifications
- The position requires detailed knowledge of the ASIC design timing closure flow and methodology. The ideal candidate will have the following background:
- Hands-on experience in ASIC timing constraints generation and timing closure.
- Expertise in STA tools (such as Primetime) and methodologies for timing closure with a good understanding of OCV, noise and crosstalk effects on timing.
- Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and BIST testing.
- Understand and implement improving existing methodologies and flows. Experience in reducing the number of timing signoff corners by merging different timing modes is helpful.
- Strong background in Constraint analysis and debug, using industry standard tools such as Synopsys CA (Constraint Analyzer).
- Knowledge of timing corners/modes, process variations and signal integrity related issues.
- Hands on experience in timing/SDC constraints generation and management.
- Knowledge of low-power techniques including clock gating, power gating and multi-voltage designs.
- Proficient in scripting languages (Tcl and Perl/Python).
- Strong interpersonal skills are a pre-requisite as the candidate will collaborate with a lot of diverse groups (e.g. digital design, DFT, physical design, etc.).
- Familiarity with synthesis, logic equivalence, DFT and backend related methodology and tools.
- Self-starter and highly motivated.
Description
Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation). Develop and maintain methodology and flows related to timing verification and closure. Generation of block and full chip timing constraints. Analyze timing reports and apply scripting techniques to develop insights and drive rapid timing closure. Work closely with various multi-functional teams on resolving complex timing issues for major building blocks of complex SoCs.
Education & Experience
BS and 3 years of relevant industry experience required.
Additional Requirements
Pay & Benefits
- At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $138,900 and $256,500, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. about Apple Benefits.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Salary : $138,900 - $256,500
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