What are the responsibilities and job description for the Senior ASIC Design Engineer position at Encore Semi, Inc.?
Position Title: Senior ASIC Design Engineer
Location: 100% remote / work from home
Full-time: Salary Benefits Bonuses or Contractor
Responsibilities:
• Architect, design and synthesize key processing blocks of automotive camera video/vision processors
• Work closely with the algorithm team to enhance efficiency and performance of next generation image processing elements
• Design of power management structures to achieve the lowest power consumption in multiple operational modes
• Develop block/system level RTL to meet synthesis/physical, DFT and power goals
• Collaborate with the physical design team to meet overall physical design targets
• Work with verification team to develop and review block and chip level verification environments and test plans
Requirements:
• BSEE with 8 years of industry experience in ASIC and SoC digital design
• Working with video/graphics processing
• Development history with neural network accelerators a plus
• Experience in RTL design with Verilog/System Verilog
• Understanding of standard ASIC design methodology with simulation, synthesis, timing closure and DFT
• Exp in 2D Graphics is an advantage
• Experience with embedded Ethernet and Ethernet MAC is an advantage
• Experience configuring & integrate RISC-V oriented Hardware Security Module IP is an advantage
• Experience developing block architecture & RTL that will meet the Functional Safety (FuSa) requirements is an advantage
• Strong programming skills in C and scripting languages such as Python
#EncoreSemi #Hiring #ASIC #ASICDesign
Location: 100% remote / work from home
Full-time: Salary Benefits Bonuses or Contractor
Responsibilities:
• Architect, design and synthesize key processing blocks of automotive camera video/vision processors
• Work closely with the algorithm team to enhance efficiency and performance of next generation image processing elements
• Design of power management structures to achieve the lowest power consumption in multiple operational modes
• Develop block/system level RTL to meet synthesis/physical, DFT and power goals
• Collaborate with the physical design team to meet overall physical design targets
• Work with verification team to develop and review block and chip level verification environments and test plans
Requirements:
• BSEE with 8 years of industry experience in ASIC and SoC digital design
• Working with video/graphics processing
• Development history with neural network accelerators a plus
• Experience in RTL design with Verilog/System Verilog
• Understanding of standard ASIC design methodology with simulation, synthesis, timing closure and DFT
• Exp in 2D Graphics is an advantage
• Experience with embedded Ethernet and Ethernet MAC is an advantage
• Experience configuring & integrate RISC-V oriented Hardware Security Module IP is an advantage
• Experience developing block architecture & RTL that will meet the Functional Safety (FuSa) requirements is an advantage
• Strong programming skills in C and scripting languages such as Python
#EncoreSemi #Hiring #ASIC #ASICDesign
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