Pre-Silicon Functional Validation Engineer @ San Jose, California

Infobahn Softworld Inc.
San Jose, CA Other
POSTED ON 4/27/2023 CLOSED ON 5/31/2023

What are the responsibilities and job description for the Pre-Silicon Functional Validation Engineer @ San Jose, California position at Infobahn Softworld Inc.?

Job Description

Title: Pre-Silicon Functional Validation Engineer - SIMICS

Location: San Jose, California

Duration: 18 Months

Onsite to start and can go remote after ramping up

Required Skills:

- Possess a Bachelor's or Master's degree in Electrical Engineering and/or Computer Engineering and/or Computer Science with 4 years of experience in the area of either hardware design or verification.

- 2 years of pre-si verification work using a validation methodology such as UVM, Specman E, VMM, AVM.

Description:

Develops pre-Silicon functional validation tests to verify system will meet design requirements.

Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests.

Analyzes and uses results to modify testing.

In this position, you will be a member of the Pre-silicon validation team in the Cloud Platform Group (CPG), responsible for functional correctness of next generation of memory buffer/controller for high end server platforms.

Your responsibility will include but not be limited to:

- Validating designs at block or full-chip level by authoring validation plans, writing focus tests, creating templates defining coverage strategies, developing and analyzing coverage monitors, creating event injectors, writing architectural and micro-architectural correctness checkers, developing BFMs (Bus Functional Model), running functional simulations, and debugging failures.

- Maintaining and enhancing the validation infrastructure by creating new tools to support validation.

- Leading a small team of engineers through any of the above.

- Working in a very team-oriented environment and interacting with engineers from other design disciplines.

This position will focus more on FPGA pre Si validation work.

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