What are the responsibilities and job description for the ASIC EDA Tool Software QA Engineer position at Intel?
Job Description
The Design Enablement ASIC Quality Assurance (QA) team is looking for qualified candidates to enhance our ASIC QA coverage for Process Design Kits (PDKs). These design kits provide collateral and flow customizations to enable Electronic Design Automation (EDA) ASIC tools and flows for the implementation and verification of silicon design products.
The selected candidate will be responsible for executing and enhancing the QA methodology and test cases which validate the ASIC collateral across multiple processes, EDA tools, and flows to ensure high-quality delivery of ASIC kit content to customers.
Responsibilities will include:
- Executing and enhancing QA methods for ASIC Design Kit collateral and design flows.
- Testcase development and support of ASIC QA test scripts.
- Analyzing and reporting Design Kit ASIC QA results.
- Working closely with ASIC collateral developers to root-cause and resolve issues.
This is an entry-level position and compensation will be given accordingly.
#DesignEnablement
Qualifications
You must possess the below minimum qualifications to be initially considered for this position.
Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Knowledge and/or experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.
Minimum Qualifications
Candidate must possess an MS degree with 6 months of experience or a PhD degree with 1 years of experience in Electrical Engineering (BSEE) or related fields with semiconductor industry ASIC design flow.
Experience with or knowledge of:
- ASIC design flows from RTL to Silicon including Synthesis, APR, GDS, DRC, Parasitic Extraction (PEX) or Static Timing Analysis (STA).
- Automated Place and Route (APR) tools including Synopsys Fusion Compiler or Cadence Innovus.
Must have the required degree or expect the required degree by the start date.
Preferred Qualifications
1 years of experience in the following:
- Linux environment capabilities and Python scripting skills.
- ASIC Test case generation skills.
- Root cause analysis skills.
- Static Timing Analysis tools including Synopsys Primetime and Cadence Tempus.
- Extraction tools including Synopsys StarRC and Cadence Quantus.
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Other Locations
US,OR,Hillsboro;US,CA,Folsom;US,CA,Santa Clara
Covid Statement
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in US, California: $102,540.00-$153,580.00
*Salary range dependent on a number of factors including location and experience
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
The Design Enablement ASIC Quality Assurance (QA) team is looking for qualified candidates to enhance our ASIC QA coverage for Process Design Kits (PDKs). These design kits provide collateral and flow customizations to enable Electronic Design Automation (EDA) ASIC tools and flows for the implementation and verification of silicon design products.
The selected candidate will be responsible for executing and enhancing the QA methodology and test cases which validate the ASIC collateral across multiple processes, EDA tools, and flows to ensure high-quality delivery of ASIC kit content to customers.
Responsibilities will include:
- Executing and enhancing QA methods for ASIC Design Kit collateral and design flows.
- Testcase development and support of ASIC QA test scripts.
- Analyzing and reporting Design Kit ASIC QA results.
- Working closely with ASIC collateral developers to root-cause and resolve issues.
This is an entry-level position and compensation will be given accordingly.
#DesignEnablement
Qualifications
You must possess the below minimum qualifications to be initially considered for this position.
Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Knowledge and/or experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.
Minimum Qualifications
Candidate must possess an MS degree with 6 months of experience or a PhD degree with 1 years of experience in Electrical Engineering (BSEE) or related fields with semiconductor industry ASIC design flow.
Experience with or knowledge of:
- ASIC design flows from RTL to Silicon including Synthesis, APR, GDS, DRC, Parasitic Extraction (PEX) or Static Timing Analysis (STA).
- Automated Place and Route (APR) tools including Synopsys Fusion Compiler or Cadence Innovus.
Must have the required degree or expect the required degree by the start date.
Preferred Qualifications
1 years of experience in the following:
- Linux environment capabilities and Python scripting skills.
- ASIC Test case generation skills.
- Root cause analysis skills.
- Static Timing Analysis tools including Synopsys Primetime and Cadence Tempus.
- Extraction tools including Synopsys StarRC and Cadence Quantus.
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Other Locations
US,OR,Hillsboro;US,CA,Folsom;US,CA,Santa Clara
Covid Statement
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in US, California: $102,540.00-$153,580.00
*Salary range dependent on a number of factors including location and experience
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
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