What are the responsibilities and job description for the Memory Design Engineer position at Intel?
Job Description
The Group:
You will be part of Intel Advanced Design Organization (AD) within Design Enablement (DE) focused on pathfinding and development of advanced memory technology and circuits to enable best-in-class memory collateral/IP and product design across all generations of Intel process technology.
Our AD organization:
- Delivers critical technology and design collaterals to enable future product designs
- Develops the 1st chips for all new Intel technology nodes
- Ensure process and design enablement are robust for high-volume product manufacturing
Critical technologies AD delivers to Intel:
- Digital and Analog Standard Cell Libraries
- Embedded Memory (SRAM, RF, ROM, eDRAM, Fuse, etc.)
- Analog Circuit Reference Designs (PLL, DLL, VR, etc.)
- High-speed I/O Reference Designs (DDR, SerDes, GPIO)
- RF and Wireless Circuits (WaveGuide TX, Power Amplifier)
- Advanced Design develops embedded memory technology, array designs, silicon testing on technologies like eDRAM, MRAM and SRAM.
The Role:
As a member of our team, your responsibilities will include (but not limited to):
- Memory pathfinding activities and power performance area (PPA) optimization through design technology co-optimization (DTCO); product/design enablement.
- Memory bitcell and complex periphery IC layout and automation
- Memory array/IP design, memory circuit innovation, testchip design/execution/validation.
- Pre/post-Si validation/debug to enable yield and parametric tracking/ramp.
#DesignEnablement
Qualifications
You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.
Minimum:
- MS or PhD in Electrical Engineering, Computer Engineering or related field.
1 year of experience in the following:
- ASIC design flow and validation
- Industry standard CAD tools/flows for digital and/or analog design
- CMOS custom circuit design, simulation, layout design and verification
- Device physics
Preferred:
- Design, characterization and verification of custom memory (SRAM, Register File, ROM) circuits
- Design trade-off of power, performance and area
- Design technology co-optimization
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Other Locations
US,TX,Austin;US,AZ,Phoenix;US,CA,Folsom;US,CA,San Jose;US,CA,Santa Clara
Covid Statement
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in US, California: $119,130.00-$178,690.00
*Salary range dependent on a number of factors including location and experience
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
The Group:
You will be part of Intel Advanced Design Organization (AD) within Design Enablement (DE) focused on pathfinding and development of advanced memory technology and circuits to enable best-in-class memory collateral/IP and product design across all generations of Intel process technology.
Our AD organization:
- Delivers critical technology and design collaterals to enable future product designs
- Develops the 1st chips for all new Intel technology nodes
- Ensure process and design enablement are robust for high-volume product manufacturing
Critical technologies AD delivers to Intel:
- Digital and Analog Standard Cell Libraries
- Embedded Memory (SRAM, RF, ROM, eDRAM, Fuse, etc.)
- Analog Circuit Reference Designs (PLL, DLL, VR, etc.)
- High-speed I/O Reference Designs (DDR, SerDes, GPIO)
- RF and Wireless Circuits (WaveGuide TX, Power Amplifier)
- Advanced Design develops embedded memory technology, array designs, silicon testing on technologies like eDRAM, MRAM and SRAM.
The Role:
As a member of our team, your responsibilities will include (but not limited to):
- Memory pathfinding activities and power performance area (PPA) optimization through design technology co-optimization (DTCO); product/design enablement.
- Memory bitcell and complex periphery IC layout and automation
- Memory array/IP design, memory circuit innovation, testchip design/execution/validation.
- Pre/post-Si validation/debug to enable yield and parametric tracking/ramp.
#DesignEnablement
Qualifications
You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.
Minimum:
- MS or PhD in Electrical Engineering, Computer Engineering or related field.
1 year of experience in the following:
- ASIC design flow and validation
- Industry standard CAD tools/flows for digital and/or analog design
- CMOS custom circuit design, simulation, layout design and verification
- Device physics
Preferred:
- Design, characterization and verification of custom memory (SRAM, Register File, ROM) circuits
- Design trade-off of power, performance and area
- Design technology co-optimization
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Other Locations
US,TX,Austin;US,AZ,Phoenix;US,CA,Folsom;US,CA,San Jose;US,CA,Santa Clara
Covid Statement
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in US, California: $119,130.00-$178,690.00
*Salary range dependent on a number of factors including location and experience
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
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