What are the responsibilities and job description for the PERC ESD CAD Engineer position at Intel?
Job Description
This position is within the Design Enablement (DE) organization of Technology Development (TD). At Intel, Design Enablement is one of the key pillars enabling Intel to deliver winning products in the marketplace.
The PERC ESD development team within this organization is looking for individuals who will be responsible to develop PERC ESD rule decks for latest Intel technologies. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies.
As part of the Design Enablement/Process Design Kit (PDK) group, you will join a highly motivated team of top-notch engineers solving challenging technical problems enabling PDKs for Intel's most advanced process technologies and drive PDKs towards industry standard methods and ease of use for the end customers.
Responsibilities include, but are not limited to the following:
- Development of ESD/LU rule decks based on Design Rule Manual (DRM) requirements.
- Creating reliability ESD and LU design rules specifications.
- Engage with internal partners and external EDA vendors to coordinate tool feature requirements and specification.
- Test-cases creation for debugging and validation.
- Define requirements for QA and related automation.
- Drive innovation and initiatives to enhance existing automation, tools, and methodology.
- Identify and analyze problems, plans, tasks, and solutions.
The candidate should also exhibit the following behavioral traits and/or skills:
- Creative, independent, and out of the box thinker with problem-solving skills and an analytical mindset.
- Attention to details, organization skills.
- Depth and Breadth, knowledge to connect the dots and identify cross-discipline optimal solutions.
- Self-motivated, leadership skills, with experience on how to influence across internal and external ecosystem.
- Written and verbal communication skills to present complex issues with clarity to drive decisions.
- Soft skills to work with cross-functional and cross site teams and influence multiple internal and external stakeholders.
- Willing to work in a dynamic and team-oriented environment.
#DesignEnablement
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must possess a BS degree with 3 years of relevant experience or MS degree with 2 years of relevant experience or PhD degree with relevant experience in Electrical Engineering or Computer Engineering.
Preferred Qualifications:
1 years of experience in the following:
- Calibre and ICV PERC tools.
- ESD/LU Pre-Si models (HBM and CDM), I/O design and methodologies.
- Debugging skills.
- Runsets, extraction and physical design domain is preferred.
- Scripting languages for QA automation.
- Experience in driving cross functional and industry wide initiatives and taskforces.
- Knowledge of semiconductor device physics, process technology, and design rules.
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Other Locations
US,Santa Clara
Covid Statement
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in US, California: $119,130.00-$178,690.00
*Salary range dependent on a number of factors including location and experience
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
This position is within the Design Enablement (DE) organization of Technology Development (TD). At Intel, Design Enablement is one of the key pillars enabling Intel to deliver winning products in the marketplace.
The PERC ESD development team within this organization is looking for individuals who will be responsible to develop PERC ESD rule decks for latest Intel technologies. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies.
As part of the Design Enablement/Process Design Kit (PDK) group, you will join a highly motivated team of top-notch engineers solving challenging technical problems enabling PDKs for Intel's most advanced process technologies and drive PDKs towards industry standard methods and ease of use for the end customers.
Responsibilities include, but are not limited to the following:
- Development of ESD/LU rule decks based on Design Rule Manual (DRM) requirements.
- Creating reliability ESD and LU design rules specifications.
- Engage with internal partners and external EDA vendors to coordinate tool feature requirements and specification.
- Test-cases creation for debugging and validation.
- Define requirements for QA and related automation.
- Drive innovation and initiatives to enhance existing automation, tools, and methodology.
- Identify and analyze problems, plans, tasks, and solutions.
The candidate should also exhibit the following behavioral traits and/or skills:
- Creative, independent, and out of the box thinker with problem-solving skills and an analytical mindset.
- Attention to details, organization skills.
- Depth and Breadth, knowledge to connect the dots and identify cross-discipline optimal solutions.
- Self-motivated, leadership skills, with experience on how to influence across internal and external ecosystem.
- Written and verbal communication skills to present complex issues with clarity to drive decisions.
- Soft skills to work with cross-functional and cross site teams and influence multiple internal and external stakeholders.
- Willing to work in a dynamic and team-oriented environment.
#DesignEnablement
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must possess a BS degree with 3 years of relevant experience or MS degree with 2 years of relevant experience or PhD degree with relevant experience in Electrical Engineering or Computer Engineering.
Preferred Qualifications:
1 years of experience in the following:
- Calibre and ICV PERC tools.
- ESD/LU Pre-Si models (HBM and CDM), I/O design and methodologies.
- Debugging skills.
- Runsets, extraction and physical design domain is preferred.
- Scripting languages for QA automation.
- Experience in driving cross functional and industry wide initiatives and taskforces.
- Knowledge of semiconductor device physics, process technology, and design rules.
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Other Locations
US,Santa Clara
Covid Statement
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in US, California: $119,130.00-$178,690.00
*Salary range dependent on a number of factors including location and experience
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
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