What are the responsibilities and job description for the Program Manager - MPS position at Intel?
About the DE organization:
It is an exciting time to join the Design Enablement (DE) organization, as we grow to meet both our internal and external product demands. DE is part of Technology Development and is one of the key pillars to enabling both internal and external design teams to deliver winning products on Intel’s cutting-edge technologies. In DE we take pride in delivering best-in-class Process Design Kits, Design Technology Co-optimization, Foundational IP, Advanced Memory, Advanced Circuit Design and Technology & IP Test Vehicles. Our mission is to enable the Design teams to get to market faster.
About the role:
The role manages multi-project shuttle programs of large cross-functional scope, impact and complexity through all phases of planning and execution. Program manager drives Multi Project Shuttle (MPS) programs to align schedules, MPS fab lot runs, technology files and runsets.
In this position, you will be responsible for program managing execution of MPS / shuttles by multiple testchip passengers. You will be expected to actively participate in shuttle roadmap planning, passenger seat allocation, coordinate alignment and tracking of multiple project schedules.
You will be responsible for aligning technology collaterals and runset across multiple projects to meet manufacturing requirements. You will need ability to resolve multiple dependencies across cross-site functional development teams. In this role, you will be required to interact and communicate with various teams and across organizations ranging from silicon design, design kits supplier, Fab and assembly.
Your responsibilities will include but are not be limited to:
Coordinate shuttle roadmap planning and passenger lists, prioritize and schedule around (internal and external) customer, manage parallel execution of MPS shuttle runs on multiple process technology nodes, reticle floorplan optimization, shuttle tapeout, despite variable request by multiple passengers/customers.
Work across a large, multi-site engineering team and negotiate with functional area managers as needed to resolve any execution issues.
Coordinate and align use of common technology collaterals and runsets across multiple MPS customers to ensure the resulting MPS meets the latest TD/fab requirements.
Monitor process technology and runset change requests and communicate changes across a broad set of MPS shuttle passengers.
Define, manage and maintain a package of standard management indicators and communicate project status across teams.
Manage and prioritize support requests, execution and inter-dependencies among multiple projects, teams and stakeholders.
The successful candidate should exhibit the following behavioral traits:
Self-disciplined, motivated and innovative, with the ability to manage tasks of broad scope and large complexity through all phases of the design cycle.
Organizational and planning skills on complex development projects
Communication and presentation skills relative to complex concepts and solutions
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum qualifications:
BS degree in Electrical Engineering, Computer Engineering, or other related field of study with 6 years of relevant experience in silicon design and/or engineering management OR a MS Degree in Electrical Engineering, Computer Engineering, or other related field of study with 4 years of related experience.
Preferred qualifications:
Prior working experience with MPS / Shuttle or test chip design tapeout desired
Proven track record of technical leadership and project execution management in the complete life cycle of a Silicon on Chip (SoC) or similar products from definition to design and tape-out
Working experiences of interfacing with process, design and design automation teams
Good understanding of leading edge process technologies, devices and the interactions with circuit design
Familiar with SoC, CPU and custom (analog and digital) design styles, flows, tools and methodologies
Familiar with EDA design software for VLSI layout and physical verification
Working fluency on process technology parameters, manufacturing steps, process characterization, physical design rules/runsets
Familiarity with database management for large, multi-site design projects
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Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art - from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.