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IC Design Verification Engineer

WinMax Systems Corporation
San Jose, CA Full Time
POSTED ON 3/19/2024
Job DescriptionIC design verification engineerSan Jose, CAFull time hire QualificationsYour primary job responsibility is to establish/enhance the verification methodology for unit-level MAC layer simulation and extend the methodology to SoC level simulation environments. In this role you will be architecting and implementing the infrastructure including test-benches, APIs, golden reference models, 802.11 specific protocol layer generators and checkers. You will also be responsible for establishing metrics and implementing tests for functional correctness, coverage, and performance characterization. Typically requires a BSCS/BSEE degree and 8 years of related experience, an MSCS/MSEE degree and 6 years of related experienceExperience building UVM based verification environments – unit-level and SoC - for 802.11, Ethernet or other networking designsKnowledge of wired or wireless networking protocols is desirableExpert knowledge of HVLs: SystemVerilog/OVM/UVM is required and OO programming experience is a plusKnowledge of assertion based (SVA, PSL based) methodologies – formal and simulation - is necessaryExperience in establishing and managing coverage requirements and achieving coverage metrics is desirableWorking knowledge of scripting in Perl, Python, Tcl, and CExperience with logic simulators and debug tools from Cadence, Synopsys, and MentorAbility to effectively collaborate with multiple teams, across geographies, in a dynamic, fast paced development environmentCapability to learn new skills or technologies as needed and be self-motivatedAdditional InformationAll your information will be kept confidential according to EEO guidelines.

Salary.com Estimation for IC Design Verification Engineer in San Jose, CA
$91,583 to $116,700
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