IP Logic Designer

Job Description

Are you passionate about designing a high-quality leading-edge IP, solving difficult problems while collaborating with a worldwide community? Joining our team as a logic design engineer may be for you! You would be joining a team chartered with delivering leading edge memory controller technology and security. We are passionate about delivering IPs that are high quality and meet our performance, timing and area goals.

Our best logic designers are able to:

• Oversee definition, design, and documentation of IP feature development
• Apply efficient coding principles for high-speed digital design
• Create microarchitecture specifications to describe logic functionality
• Code Verilog designs to match the required specifications
• Utilize industry standard design tools to ensure high quality designs
• Evaluate timing and power reports to ensure design requirements are achieved
• Collaborate with verification team to achieve a high quality functionally correct design
• Communicate with Intel development community on design functionality
• Debug issues to root cause, including supporting pre- and post-silicon validation teams

Key skills and experience may include:

• Understanding memory traffic protocols, data encryption and secure design principles
• Design development using Verilog/SystemVerilog
• Writing and debugging System Verilog Assertions (SVA)
• Interpreting code coverage results
• Collaboration with verification partners
• Working in environments that include use of constrained-random stimulus and functional coverage

• • Open Verification Methodology (OVM)/Universal Verification Methodology (UVM)

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Bachelor's degree in Electrical/Computer Engineering or Computer Science and 4 years experience.
OR

Master's degree in Electrical/Computer Engineering or Computer Science and 3 years experience.

• Experience in IP or SOC design using Verilog or System Verilog.

Preferred Qualifications:

• Experience in development of memory controllers for DDR or HBM memory technologies.

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, California, Santa Clara;US, Oregon, Hillsboro;US, Texas, Austin

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range for jobs which could be performed in US, Colorado:
$113,500.00-$170,120.00

Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.