SoC Floorplan Lead

Job Description

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are

Come join the Discrete Graphics Artificial Intelligence (DGAI) team! We are responsible for Physical Implementation of the Graphics AI products at Intel.

Who You Are

SoC Floorplan Lead will drive floorplan activities like:

• Working with micro-architecture, estimate die-area based on Std Cell area and RAM design: also based on right process node and features set
• Define optimal physical dimensions for SoC by including product costs like die-per-reticle, right technology selection/metal stack and reuse from existing product family.
• Derive optimal placement of IO blocks based on platform and package constraints
• Evaluate multiple floorplan options and Sub-system placement based on dataflow analysis and area estimates, clocking/voltage domain requirements
• Drive execution, and supervise progress of smaller sub-systems influencing their physical placement, shape, and channel planning to help them achieve best area and convergence schedule. Plan short and long-term work schedule, understanding dependencies between different hierarchies like fullchip, sub-system and blocks.
• Collaborate with other stake holders like: with the clock design to deliver the physical block level floorplans for APR and with the power delivery team on tradeoffs for metal allocation for signal and power.
• Drive methodologies, tools and best known methods with Flow team to streamline Floorplan Physical Design work to achieve best-in-class on schedule delivery.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

What we need to see (Minimum Qualifications):

• Possess Bachelor's degree in Electrical Engineering, Computer Engineering or similar field with 8 years' of relevant experience OR MS degree in Electrical Engineering, Computer Engineering or similar field with 5 years' of relevant experience OR PhD degree in Electrical Engineering, Computer Engineering or similar field with 3 years' of relevant experience.

• Expert in ASIC integration including Floorplanning, Clock and Power distribution, Global signal planning, I/O planning and Macro placement.

• Expert knowledge of SoC Floorplan requirements like multiple voltage and clock domains, Level Shifters, thermal management, Die-to-Die interconnects, and package interactions.

• Expertise with Floorplanning tools – ICC2/FC, Place and Route flows, and Physical Design Verification Flows and process nodes 5nm or below.

• Sound understanding in hierarchical design approach, top-down design, handling MIB (multiple instantiation blocks), and physical convergence.

How to Stand out (Preferred Qualifications):

• Good experience with large subsystem designs (20M gates) with frequencies >2GHz.

• Great automation skills/focus with coding familiarity in tcl/perl/python

• GPU/AICore Data-flow understanding and familiarity is an added advantage.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations

US, TX, Austin; US, AZ, Phoenix; US, CA, Folsom

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Annual Salary Range for jobs which could be performed in US, California: $162,041.00-$259,425.00

• Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

JobType

Hybrid