Senior ASIC Design Engineer Salary at Chain Reaction Bicycles BETA

Job Description Job Description About Etched Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real time video generation models and extremely deep chain-of-thought reasoning. Title: Principal Design Verification Engineer Job Duties: Develop ASIC testbenches using advanced verification methodologies such as UVM to verify the correct functionality of microchip design. Implement micro-architecture and RTL specifications using System Verilog and maintain the verification environment for the specialized AI microchips, considering system-level test scenarios and coverage plans. Execute functional and performance verification of microchip design, employing synthesized netlists, coverage models, and tools such as Synopsys VCS and Verdi. Work in close

Job Description Job Description About Etched Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep chain-of-thought reasoning. ECAD/MCAD Symbol Librarian We are seeking an experienced ECAD/MCAD Librarian to manage and maintain our symbol and component libraries, ensuring seamless integration between electrical and mechanical design workflows while supporting design for manufacturability (DFM). Representative Projects: Develop, maintain, and organize both the ECAD library for Allegro Layout PCB footprints and the MCAD library for Siemens NX, ensuring alignment with design team requirements and project specifications Create and validate complex schematic symbols and PCB footprints for Allegro Layo

Job Description Job Description Design Verification Engineer Etched is building the hardware for superintelligence. GPUs and TPUs are flexible AI chips that can run many kinds of models: CNNs, RNNs, LSTMs, and more. But today, almost all AI workloads, from ChatGPT to self-driving cars, are done on one model architecture: transformers. Using flexible AI chips for transformers is very inefficient: <5% of the transistors on an H100 are used for matrix multiplication! Etched is building a single-purpose chip exclusively for transformer inference. We only support transformers, but in exchange our chips have an order of magnitude more throughput and lower latency than an H100. With Etched, you can build products that would be impossible with GPUs, like tree-of-thought agents and ultra-low-latency audio chat bots. We are seeking highly motivated Principal Verification Engineers to join our team. Our verification This role will report to the VP of Hardware Engineering. Responsibilities: Ensure

Senior ASIC Physical Design Engineer Are you an experienced ASIC engineer ready to lead the way in generative AI inference acceleration? Join our team and help shape the future of cutting-edge technology. This is a hands-on leadership role where you’ll drive innovation and develop scalable, high-performance systems in a fast-paced, agile environment. What You’ll Do: Lead front-end physical design and workflow development for AI inference acceleration products. Optimize and implement advanced workflows, including synthesis, formal checks, power analysis, and STA. Collaborate closely with cross-functional teams to enhance productivity and address complex EDA challenges. Utilize industry-standard tools like Cadence and Synopsys while exploring new methodologies. Support backend teams with clock trees, routing, DRC, LVS, and more. What We’re Looking For: Experience: 10+ years of hands-on ASIC engineering experience, with deep knowledge of VLSI/SoC physical design workflows. Skills: Profici

Job title: Senior Physical Design Architect Location: San Jose, CA Duration: Full Time (Permanent) Job Description: Work closely with logic design team to define physical architecture and drive physical aspects during the design cycle. Collaborate across teams (physical design, logic design, package, DFT and test). Hands-on synthesis and PnR using industry standard tools for high-speed digital designs in advanced process nodes. Perform all aspects of sign-off including power, timing, physical verification checks, and design closure. Must have experience: 15-20 years of experience in Physical Design and timing closure. Hands-on experience in synthesis, PnR and STA using Cadence/Synopsys tools for complex digital designs in 7nm and below. Must have experience of multiple large SoC tapeouts in advanced nodes including hands-on experience in chip-level physical design and STA closure. Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at bl

Software Engineer, Accelerator Solutions & Technologies Apply to this job Location pin icon Menlo Park, CA Apply to this job Meta is seeking an experienced software engineer to join our Accelerator Solutions & Technologies group, supporting the development of Meta's accelerators collective communications software library and optimizing distributed AI/ML workloads' performance. This is an opportunity to work with a highly skilled engineering team, collaborating with a large set of cross-functional and international partners. Meta's super-cluster AI/ML platforms offer the opportunity to work in an extremely dynamic environment, enabling core technologies deployed in some of the world's largest scale clusters. Software Engineer, Accelerator Solutions & Technologies Responsibilities Contribute to our developer infrastructure, including simulation and HW emulation platforms, to enable performance measurement and optimization for Meta's in-house accelerator programs. Understand and contribut

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: We are seeking for an experienced RTL Designer for our team. The engineer will be responsible for design & development of digital circuits including defining the architecture. Requirements: Bechelor's Degree in Electrical Engineering, Computer Engineering or Computer Science and 8+ years of meaningful experience in SOC architecture and design experience or Master's Degree in Electrical Engineering, Computer Engineering, or Computer Science and 6+ years of meaningful experience in SOC architecture and design experience. Verification experience is a plus. Experience in micro-architecture and RTL development. Worked on architecture definitions on clocks, resets, interconnects, IO interfaces. Worked on ARM based SoC Should have knowledge on Lint, CDC

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the worlds most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: THE ROLE: AMD is looking for dynamic and energetic SR Engineer Program Manager to join our NTSG - Network Technology Solutions Group. Our team fosters continuous innovation and is committed to nurturing your career growth. THE PERSON: You will provide support for our NTSG Network Technology Solutions Group and join the team that is responsible for readying our har